O'Melveny Represents AutoESL Design Technologies in Aquisition by Xilinx Inc.一月 31, 2011
FOR IMMEDIATE RELEASE
Andrea Rodeschini Julie Fei
O’Melveny & Myers LLP O’Melveny & Myers LLP
SILICON VALLEY, CALIFORNIA ─ JANUARY 31, 2011 ─ O’Melveny & Myers LLP represented AutoESL Design Technologies, Inc., the leading provider of high level synthesis for FPGAs and ASICs in its acquisition by Xilinx, the worldwide leader in complete programmable logic solutions.
The O’Melveny deal team was led by Silicon Valley partners Paul Sieben and Warren Lazarow and counsel Jeff Cislini.
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The following press release was recently issued by Xilinx:
Xilinx Acquires AutoESL to Enable Designer Productivity and Innovation With FPGAs and Extensible Processing Platform
SAN JOSE, Calif., Jan. 31, 2011 /PRNewswire via COMTEX/ -- Xilinx, Inc. (Nasdaq: XLNX), the world's leading provider of programmable platforms, today announced the acquisition of high level synthesis leader AutoESL Design Technologies, Inc.
Expanding Xilinx's technology foundation and product portfolio to include high level synthesis will enable the company to deliver the benefits of programmable platforms to a broader base of companies where system architects and hardware designers are accustomed to designing at a higher level of abstraction in C, C++ and System C. It will also enable Xilinx to address growing customer demand for tools that support electronic system-level (ESL) design methodologies for today's complex designs targeted in field-programmable gate arrays (FPGAs).
AutoESL's flagship high level synthesis tool, AutoPilot, has been adopted by leading semiconductor and systems companies to enhance productivity and speed time-to-market for video, wireless, and high performance computing applications, of whom more than 25 are Xilinx customers and Alliance Program members. With today's announcement, Xilinx intends to increase designer productivity and innovation with its 6 series and 7 series FPGAs and new Extensible Processing Platform.
"Xilinx has incubated high-level synthesis technology for many years," said Vin Ratford, senior vice president of worldwide marketing at Xilinx. "In 2006, we launched our ESL initiative with a goal to help the industry improve quality of results, simplify and abstract design flows, establish interoperability and improve embedded processing flows.
"Recently, we commissioned an independent study to evaluate high-level synthesis tool offerings. Based upon benchmarks conducted by BDTI as well as Xilinx Research Labs, it was clear that AutoPilot's quality of results matched or exceeded hand-coded RTL for data path-intensive and DSP designs. We're delighted to welcome the AutoESL team to Xilinx. Together, I have every confidence we'll deliver on the promise of FPGA-based electronic system-level design." Xilinx did not disclose terms of the acquisition. The majority of AutoESL employees currently located at the company's headquarters in Cupertino, California and Beijing, China, will become Xilinx employees.
"Historically, demanding applications implemented in handwritten RTL code on an FPGA typically achieved relatively good quality of results but poor productivity, while applications implemented on DSP processors provided good productivity but relatively poor quality of results," according to Jeff Bier, founder and president of BDTI (Berkeley Design Technology, Inc.) in Xcell Journal magazine (second quarter 2010).
"Development time has been a key impediment for many system designers trading off the use of a programmable DSP processor vs. an FPGA. Our evaluation indicates that this new approach involving high-level synthesis tools largely eliminates this barrier for applications, such as the BDTI Optical Flow Workload." BDTI created the BDTI High-Level Synthesis Tool Certification Program to provide objective, credible data and analysis to enable potential users of high-level synthesis tools for FPGAs to quickly understand the capabilities and limitations of these tools. For more information, see BDTI AutoPilot benchmark results and BDTI High-level Synthesis white paper.
About the AutoPilot High Level Synthesis Tool for Xilinx FPGAs The AutoPilot high level synthesis tool is optimized for Xilinx FPGA architectures and intelligently generates register transfer-level (RTL) code that produces the best possible QoR to meet throughput, power, area and timing design goals. It also reduces verification time by orders of magnitude due to the advantage of working at a higher level of abstraction in C, C++ or SystemC.
Xilinx's new Virtex(R)-7 family of devices provides up to 2M logic cells and 4000 DSP48E1 slices. The combination of AutoPilot high level synthesis and plug-and-play IP will reduce development time for customers who model in C, C++ or SystemC.
With high level synthesis, embedded designers using Xilinx's new Extensible Processing Platform will be able to more seamlessly partition designs between the ARM(R) Cortex(TM)-A9 MPCore processor and the programmable logic. The combination of AutoPilot and ISE(R) Design Suite will enable system architects, hardware designers and, in the future, embedded software developers to apply a combination of serial and parallel processing to address the challenging system requirements presented by the global demand for embedded systems to perform increasingly complex functions.
In the first half of 2011, a new Xilinx-only version of AutoPilot will be available to customers. In the future, AutoPilot will be an option for the company's ISE Design Suite software.
About the Xilinx Platform Strategy Given the sophistication of today's programmable platforms and diverse set of application requirements Xilinx serves, it is no longer feasible for a single design flow or environment to fit every designer's need. System designers, algorithm designers, software coders, and logic designers each represent a different user profile or persona with unique requirements for a design methodology and associated design environment.
Rather than providing fixed tools, Xilinx strategy is to match each user profile to a preferred methodology and design flow. At the system-level, C, C++, SystemC, and MATLAB(R) are most widely used, as the level of design abstraction moves up from HDL (VHDL/Verilog) at the component level.
The result is a methodology and complete design flow tailored to each user profile for design creation, design implementation, and design verification. Altogether, plug-and-play IP, targeted reference designs, development boards, design services and support from the Alliance Program ecosystem create a powerful foundation for customers to fully exploit the benefits of Xilinx programmable platforms.
About AutoESL Design Technologies, Inc.
AutoESL Design Technologies, Inc. is the leading provider of high level synthesis for FPGAs and ASICs. The company was founded in 2006 based on advanced proprietary technology that was originally developed at UCLA. AutoESL has now deployed this solution at many leading edge system and semiconductor companies. The company is located in Cupertino, California, and has design centers in Beijing, China. For more information, see www.autoesl.com.
About Xilinx Xilinx is the world's leading provider of programmable platforms. For more information, visit www.xilinx.com.
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